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soc_rp2040::watchdog

RP2040 watchdog control and retained reset reason.

The load conversion follows the Pico SDK and NuttX: RP2040-E1 makes the counter decrement twice per watchdog tick, so one millisecond is 2,000 load counts when the tick generator runs at 1 MHz.

unsafe fn arm(timeout_ms: u32, pause_on_debug: bool)

Start the watchdog. The debugger may optionally pause its counter.

Changes reset routing and commits the chip to resetting at the timeout.

unsafe fn arm_panic_recovery(timeout_ms: u32)

Start a watchdog reset that reboots the application once before BOOTSEL.

Commits the chip to resetting at the timeout and changes retained scratch state.

unsafe fn clear_flint_watchdog_marker()

Clear FlintOS’s retained marker after consuming the reset report.

Writes a retained scratch register used by reset handling.

unsafe fn disarm()

Stop the watchdog.

Disables automatic recovery from a stopped kernel.

unsafe fn feed(timeout_ms: u32)

Reload the armed watchdog.

Writes the live watchdog counter and must use the timeout policy of its owner.

unsafe fn flint_watchdog_caused_reset() -> bool

Whether FlintOS armed the watchdog before the retained reset.

Reads memory-mapped reason and scratch registers.

const fn load_for_ms(timeout_ms: u32) -> u32

Convert milliseconds to the RP2040-E1-adjusted counter load.

unsafe fn reset_reason() -> u32

Raw retained reason bits: timer is bit 0 and forced reset is bit 1.

Reads a memory-mapped hardware register.

const fn reset_reason_name(reason: u32) -> &'static str
const FLINT_PANIC_REBOOT_MARKER: u32;

Requests one direct flash reboot so a panic snapshot remains in SRAM.

const FLINT_WATCHDOG_MARKER: u32;

Pico SDK’s non-reboot marker. Its intentional reboot path clears this, which distinguishes a timeout from UF2 flashing and ROM USB reboot.