soc_esp32::addr

ESP32 peripheral base addresses and interrupt sources.

These belong to the chip, not to a board. Two boards carrying the same ESP32 have the same UART0 at the same address; what differs is which pins it comes out on. Board manifests used to spell these out as hex literals, which meant a typo in one board file was invisible from every other.

Confirmed against esp-idf soc/soc.h and soc/soc_caps.h.

Functions

i2c_instance

const fn i2c_instance(base: u32) -> Option<u8>

Controller instance for an I2C base address.

spi_instance

const fn spi_instance(base: u32) -> Option<u8>

Controller instance for an SPI base address.

SPI1 is deliberately absent: it drives the boot flash, and handing it to a general-purpose driver bricks the running image.

uart_instance

const fn uart_instance(base: u32) -> Option<u8>

Controller instance for a UART base address.

Constants

AES_BASE

const AES_BASE: u32;

DR_REG_AES_BASE. The AES accelerator. Lives inside the DPORT window, so its registers take the erratum-safe DPORT access, not plain volatile.

DPORT_BASE

const DPORT_BASE: u32;

EFUSE_BASE

const EFUSE_BASE: u32;

eFuse controller. Block 0 holds the factory MAC address, among much else.

GPIO_BASE

const GPIO_BASE: u32;

I2C0_BASE

const I2C0_BASE: u32;

I2C0. I2C1 is a wholly separate register block, not I2C0 + 0x20.

I2C1_BASE

const I2C1_BASE: u32;

IO_MUX_BASE

const IO_MUX_BASE: u32;

IRQ_GPIO

const IRQ_GPIO: u8;

IRQ_I2C0

const IRQ_I2C0: u8;

IRQ_I2C1

const IRQ_I2C1: u8;

IRQ_LEDC

const IRQ_LEDC: u8;

ETS_LEDC_INTR_SOURCE. Fade-complete and timer overflow; unused so far.

IRQ_RMT

const IRQ_RMT: u8;

47, not 46. Checked against ETS_RMT_INTR_SOURCE.

IRQ_SPI1

const IRQ_SPI1: u8;

IRQ_SPI2

const IRQ_SPI2: u8;

IRQ_SPI3

const IRQ_SPI3: u8;

IRQ_TIMG0_T0

const IRQ_TIMG0_T0: u8;

Timer-group alarms. One source per timer, not one per group — from ETS_TG0_T0_LEVEL_INTR_SOURCE onward in esp-idf soc/periph_defs.h.

The _LEVEL_ sources, not the _EDGE_ ones: the kernel’s crossbar only hands out level-triggered CPU inputs, and intr_map::route refuses the rest rather than routing something it could not service.

IRQ_TIMG0_T1

const IRQ_TIMG0_T1: u8;

IRQ_TIMG1_T0

const IRQ_TIMG1_T0: u8;

IRQ_TIMG1_T1

const IRQ_TIMG1_T1: u8;

IRQ_UART0

const IRQ_UART0: u8;

IRQ_UART1

const IRQ_UART1: u8;

IRQ_UART2

const IRQ_UART2: u8;

LEDC_BASE

const LEDC_BASE: u32;

DR_REG_LEDC_BASE. PWM: eight high-speed channels over four timers.

PCNT_BASE

const PCNT_BASE: u32;

DR_REG_PCNT_BASE. Pulse counter: eight units with glitch filtering.

RMT_BASE

const RMT_BASE: u32;

RTC_CNTL_BASE

const RTC_CNTL_BASE: u32;

SHA_BASE

const SHA_BASE: u32;

DR_REG_SHA_BASE. The SHA accelerator. Also inside the DPORT window.

SPI1_BASE

const SPI1_BASE: u32;

SPI1, the controller wired to the boot flash. Not for general use.

SPI2_BASE

const SPI2_BASE: u32;

SPI2, exposed as “HSPI”.

SPI3_BASE

const SPI3_BASE: u32;

SPI3, exposed as “VSPI”.

TIMG0_BASE

const TIMG0_BASE: u32;

TIMG1_BASE

const TIMG1_BASE: u32;

UART0_BASE

const UART0_BASE: u32;

UART1_BASE

const UART1_BASE: u32;

UART2_BASE

const UART2_BASE: u32;