soc_esp32::ctrl

Peripheral controllers as types, and the ports that bind one to a pin configuration.

A driver used to be constructed from a bare u32 base address and then re-derive everything else about its controller at run time: its instance number through addr::spi_instance on every transfer, its clock bit through dport::clock_bit at init, its interrupt source from a board-manifest field that could disagree with the base. [I2cCtrl], [SpiCtrl] and [UartCtrl] close the enum once: every attribute is a const fn of the variant, evaluated from the same addr and dport constants the rest of the crate uses, and an invalid combination cannot be spelled.

SPI1 is deliberately not a [SpiCtrl] variant. It drives the boot flash and addr::spi_instance already refuses it; the DMA crossbar’s dma::Host keeps a Spi1 variant only because the hardware has a selector field for it.

The port structs pair a controller with its pin configuration so an app passes one Copy value instead of a base, an instance and a config that have to agree. Each carries the per-bus config type that matches its controller — an [I2cPort] holds an [I2cConfig], never a SPI one — so a mismatch is a type error rather than a run-time InvalidConfig.

Structs

I2cPort

struct I2cPort {
    pub ctrl: I2cCtrl,
    pub cfg: hal::bus::I2cConfig,
}

An I2C controller and the pin configuration it is to be brought up with.

Implements: Clone, Copy, Debug

References: I2cConfig, I2cCtrl

SpiPort

struct SpiPort {
    pub ctrl: SpiCtrl,
    pub cfg: hal::bus::SpiConfig,
}

A SPI controller and the pin configuration it is to be brought up with.

Implements: Clone, Copy, Debug

References: SpiConfig, SpiCtrl

UartPort

struct UartPort {
    pub ctrl: UartCtrl,
    pub cfg: hal::bus::UartConfig,
}

A UART controller and the pin configuration it is to be brought up with.

Implements: Clone, Copy, Debug

References: UartConfig, UartCtrl

Enums

I2cCtrl

enum I2cCtrl {
    I2c0,
    I2c1,
}

One of the two I2C controllers.

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq

SpiCtrl

enum SpiCtrl {
    Spi2,
    Spi3,
}

One of the two general-purpose SPI controllers.

SPI1 is absent on purpose: it is wired to the boot flash.

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq

UartCtrl

enum UartCtrl {
    Uart0,
    Uart1,
    Uart2,
}

One of the three UART controllers.

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq