soc_rp2040::dma

RP2040’s twelve uniform DMA channels.

Channel ownership and register programming live with the SoC. Physical drivers choose a peripheral DREQ and hand this module broker-validated SRAM addresses; they never name DMA registers. The abort sequence follows Pico SDK’s dma_channel_cleanup: disable completion delivery first, abort, then clear the RP2040-E13 late completion before another owner can claim the channel.

Structs

Channel

struct Channel { /* private fields */ }

Implements: Debug, Drop

Dreq

struct Dreq(/* private */);

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq

TransferConfig

struct TransferConfig {
    pub direction: Direction,
    pub memory_addr: u32,
    pub peripheral_addr: u32,
    pub count: u32,
    pub dreq: Dreq,
}

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq

References: Direction, Dreq

Enums

Direction

enum Direction {
    MemoryToPeripheral,
    PeripheralToMemory,
}

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq

Error

enum Error {
    NoChannelFree,
    InvalidChannel,
    InvalidRange,
    InvalidCount,
    StaleChannel,
    CompletionBusy,
    HardwareFault,
}

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq

Functions

claim

fn claim() -> Result<Channel, Error>

References: Channel, Error

claim_number

fn claim_number(number: u8) -> Result<Channel, Error>

References: Channel, Error

start_mask

fn start_mask(channels: u32) -> Result<(), Error>

References: Error

take_irq0

fn take_irq0() -> u32

take_irq0_completion

fn take_irq0_completion() -> Option<u32>

Acknowledge one IRQ0 channel and take the completion token it published. Clearing one bit at a time leaves any concurrent completion asserted so the NVIC re-enters and no channel’s broker notification is lost.

Constants

CHANNELS

const CHANNELS: u8;