soc_rp2040

RP2040 chip facts used before peripheral drivers exist.

Addresses and interrupt numbers are from the Raspberry Pi RP2040 datasheet, sections 2.2 (address map) and 2.3 (interrupts), build 3184e8e (2025-02-20). The SRAM extent is the six-bank 264 KiB window.

Modules

• boot2 — W25Q080-compatible RP2040 second-stage bootloader.
• ctrl — Typed RP2040 peripheral identities and cross-core ownership claims.
• dma — RP2040’s twelve uniform DMA channels.
• multicore — RP2040 SIO primitives and the ROM core-1 launch protocol.
• pinmux — RP2040 fixed-function pin routing.
• test_status — Machine-observable completion for ARM on-target tests.
• watchdog — RP2040 watchdog control and retained reset reason.
• xip — Two-core exclusion for operations which temporarily remove flash/XIP.

Structs

Rp2040

struct Rp2040;

Implements: LowPower, PanicRecovery, SystemOnChip

Rp2040Dma

struct Rp2040Dma;

Implements: DmaReach

Functions

enable_adc_clock

fn enable_adc_clock()

Select the crystal for clk_adc and enable the clock slice.

The ADC’s reset-done bit cannot rise while this clock is stopped. Keep its 12 MHz crystal source independent of the optional USB/CPU PLL profile.

enable_peripheral_clock

fn enable_peripheral_clock()

Keep peripherals on the 12 MHz crystal even when USB raises the CPU clock.

reset

unsafe fn reset(mask: u32)

Assert reset for one or more peripheral blocks through the atomic set alias.

Safety

The caller must exclusively own the selected blocks and ensure no other core or interrupt uses them. Any in-flight operation is discarded.

uart_instance

fn uart_instance(base: u32) -> Option<u8>

unreset

unsafe fn unreset(mask: u32)

Release peripherals from reset through the atomic clear alias.

Safety

The caller must ensure each requested peripheral is ready before use.

Constants

ADC_BASE

const ADC_BASE: u32;

CPU_HZ

const CPU_HZ: u32;

DMA_BASE

const DMA_BASE: u32;

I2C0_BASE

const I2C0_BASE: u32;

I2C1_BASE

const I2C1_BASE: u32;

IO_BANK0_BASE

const IO_BANK0_BASE: u32;

IRQ_ADC_FIFO

const IRQ_ADC_FIFO: u8;

IRQ_DMA_0

const IRQ_DMA_0: u8;

IRQ_DMA_1

const IRQ_DMA_1: u8;

IRQ_I2C0

const IRQ_I2C0: u8;

IRQ_I2C1

const IRQ_I2C1: u8;

IRQ_IO_BANK0

const IRQ_IO_BANK0: u8;

IRQ_PWM_WRAP

const IRQ_PWM_WRAP: u8;

IRQ_SPI0

const IRQ_SPI0: u8;

IRQ_SPI1

const IRQ_SPI1: u8;

IRQ_UART0

const IRQ_UART0: u8;

IRQ_UART1

const IRQ_UART1: u8;

IRQ_USBCTRL

const IRQ_USBCTRL: u8;

NVIC_IRQ_COUNT

const NVIC_IRQ_COUNT: u8;

PADS_BANK0_BASE

const PADS_BANK0_BASE: u32;

PWM_BASE

const PWM_BASE: u32;

RESETS_BASE

const RESETS_BASE: u32;

RESET_ADC

const RESET_ADC: u32;

RESET_DMA

const RESET_DMA: u32;

RESET_I2C0

const RESET_I2C0: u32;

RESET_I2C1

const RESET_I2C1: u32;

RESET_IO_BANK0

const RESET_IO_BANK0: u32;

RESET_PADS_BANK0

const RESET_PADS_BANK0: u32;

RESET_PWM

const RESET_PWM: u32;

RESET_SPI0

const RESET_SPI0: u32;

RESET_SPI1

const RESET_SPI1: u32;

RESET_UART0

const RESET_UART0: u32;

RESET_UART1

const RESET_UART1: u32;

RESET_USBCTRL

const RESET_USBCTRL: u32;

ROSC_BASE

const ROSC_BASE: u32;

SIO_BASE

const SIO_BASE: u32;

SPI0_BASE

const SPI0_BASE: u32;

SPI1_BASE

const SPI1_BASE: u32;

SRAM_BASE

const SRAM_BASE: u32;

SRAM_END

const SRAM_END: u32;

SRAM_SIZE

const SRAM_SIZE: u32;

UART0_BASE

const UART0_BASE: u32;

UART1_BASE

const UART1_BASE: u32;

USB_DPRAM_BASE

const USB_DPRAM_BASE: u32;

USB_REGS_BASE

const USB_REGS_BASE: u32;

XIP_BASE

const XIP_BASE: u32;

XIP_SIZE

const XIP_SIZE: u32;

XOSC_HZ

const XOSC_HZ: u32;

Crystal shared by the supported Wio RP2040 and Raspberry Pi Pico boards.