esp32_adc2

ADC2: ten channels of analog input, sharing their SAR with the Wi-Fi radio.

Why this is a separate crate from ADC1

ADC2’s converter, SAR2, is the same block the Wi-Fi PHY borrows for RF power detection and calibration. While the radio owns it a software conversion returns garbage or never completes. An API that hands out ADC2 channels with no interlock invites a bug that appears the day someone turns on networking and not before — the worst kind. So read takes the radio’s state as an argument and refuses with [Adc2Error::RadioBusy] when it is up.

The state is passed in rather than imported deliberately: this crate must not depend on the radio crate (that would be a dependency cycle, radio → drivers → radio), and the radio is the only thing that knows whether it is running. The caller holds both and connects them. See issue #75.

These channels overlap the DAC and a lot of strapping pins

Channel 8 is GPIO 25 is DAC1; channel 9 is GPIO 26 is DAC2. That shared pad is what a DAC→ADC2 loopback test uses — drive the DAC, read it back on the same pin with no wire. Several other ADC2 pins are boot-strapping or JTAG pins and are not free to use on a DevKitC without care.

Raw counts, not volts; attenuation as on ADC1

Same as esp32-adc: readings are raw 12-bit SAR counts, not millivolts, and the input range depends on the per-channel attenuation. See that crate’s docs for the attenuation table.

Register facts

DR_REG_SENS_BASE = 0x3FF48800, DR_REG_SYSCON_BASE = 0x3FF66000, from esp-idf soc/soc.h. Fields from soc/sens_reg.h and soc/syscon_reg.h; the RTC-control sequence from hal/adc_ll.h adc_ll_set_controller.

Register	Address	Fields
SAR_MEAS_WAIT2	0x3FF4880C	FORCE_XPD_SAR [19:18], FORCE_XPD_AMP [17:16]
SAR_MEAS_CTRL	0x3FF48810	amplifier FSM [15:4]
SAR_ATTEN2	0x3FF48838	two bits per channel
SAR_READ_CTRL2	0x3FF48890	SAR2_SAMPLE_BIT [17:16], SAR2_PWDET_FORCE 27, SAR2_DIG_FORCE 28, SAR2_DATA_INV 29
SAR_MEAS_START2	0x3FF48894	EN_PAD_FORCE 31, EN_PAD [30:19], START_FORCE 18, START_SAR 17, DONE_SAR 16, DATA_SAR [15:0]
SYSCON_SARADC_CTRL	0x3FF66010	SAR2_MUX 2

Structs

Adc2

struct Adc2 { /* private fields */ }

ADC2, taken as a whole. One instance: the channels share SAR2 and one set of control registers.

Enums

Adc2Error

enum Adc2Error {
    Timeout,
    RadioBusy,
}

Why a reading failed.

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq

Channel

enum Channel {
    Gpio4,
    Gpio0,
    Gpio2,
    Gpio15,
    Gpio13,
    Gpio12,
    Gpio14,
    Gpio27,
    Gpio25,
    Gpio26,
}

An ADC2 channel, named by the GPIO it reads. The channel number is not the GPIO number and not pin order — channel 0 is GPIO 4.

Implements: Clone, Copy, Debug, Eq, PartialEq, StructuralPartialEq