esp32_crypto::aes

The ESP32 AES accelerator: single-block AES-128/256 ECB.

One 16-byte block in, one out. This is the raw block transform — no chaining mode, no padding. ECB of a single block is exactly what a mode built on top (CBC, CTR, the CCM/CMAC in the crypto lib) needs as its primitive, and it is the cleanest thing to check against a known-answer vector.

Sequence (esp-idf aes_hal.c / aes_ll.h)

Per block: write MODE (which encodes encrypt/decrypt and key length), write the key words, write the four input words, pulse START, wait until IDLE reads 1, then read the four output words. The hardware holds no state between blocks, so the key and mode are rewritten every call — which is why an [Aes] just stores the key bytes rather than a schedule.

Byte order

The opposite of SHA. esp-idf’s block path writes key and text words straight through with DPORT_REG_WRITE of a little-endian load and reads the output back the same way — no swap anywhere (aes_ll_write_key, aes_ll_write_block, aes_ll_read_block). So every word here is u32::from_le_bytes / to_le_bytes, and the AES_ENDIAN register is left at its reset default, exactly as the esp-idf block driver leaves it.

Structs

Aes

struct Aes { /* private fields */ }

The AES accelerator, bound to one key.

Cheap to construct — it only remembers the key bytes; the hardware is touched per block, not here.

Enums

AesKey

enum AesKey {
    Bits128([u8; 16]),
    Bits256([u8; 32]),
}

An AES key: 128- or 256-bit. (192-bit is legal on the hardware too, but the software lib the driver is checked against ships only 128 and 256, so those are the two offered here.)

Implements: Clone, Copy, Debug