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esp32_timg::lact

The LAC timer — a timer group’s fifth counter, and a programmable alarm.

Each timer group documents two general-purpose timers, and the ESP32 has two groups, so four in total. FlintOS has all four spoken for: TIMG1/T1 is kernel::clock, and TIMG0/T0, TIMG0/T1 and TIMG1/T0 drive on-target self-tests.

The LAC (“low-power/ALARM counter”) is a separate 64-bit up-counter inside the same register block, at offsets 0x70..0x94, with its own alarm compare and its own interrupt bit. esp-idf’s esp_timer runs on exactly this counter, on TG0, for exactly this reason — see components/esp_timer/src/esp_timer_impl_lac.c, whose header says so in as many words. NuttX reaches the same hardware through esp-idf’s esp_timer. So using it here costs no general-purpose timer and follows the reference rather than diverging from it.

The counter is clocked from APB through a 16-bit divider. esp-idf uses TICKS_PER_US = 2 and comments the reason: at one tick per microsecond the counter needs up to a microsecond of settling after UPDATE before it can be read, which makes reading the time too slow. Two ticks per microsecond divides evenly into every APB frequency Espressif ships and halves that wait. Copied, including the value.

No sleep support. esp-idf also programs LACTRTC so the counter keeps time from the RTC slow clock across light sleep; FlintOS has no sleep (#31), and a register written for a mode that cannot be entered is a claim about behaviour nobody can check.

struct Lact { /* private fields */ }

One group’s LAC timer.

const LACT_INT: u32;

The LAC timer’s bit in the group’s interrupt registers. Bit 3, after the two general-purpose timers and the watchdog.

const TG0_LACT_INTR_SOURCE: u8;

ETS_TG0_LACT_LEVEL_INTR_SOURCE. The crossbar input this raises.

const TG1_LACT_INTR_SOURCE: u8;

ETS_TG1_LACT_LEVEL_INTR_SOURCE.

const TICKS_PER_US: u64;

Counter ticks per microsecond. esp-idf’s TICKS_PER_US; see the module docs for why it is not 1.