soc_esp32::reset

Why the chip last reset.

The hardware records this and it survives the reset, which makes it the only direct evidence available after the fact. Everything else — how long the board ran, what the last line on the console was — is inference.

This exists because two rounds of reasoning about which watchdog was resetting a board produced two wrong answers. The register says.

Values from esp-idf’s esp_reset_reason_t mapping over RTC_CNTL_RESET_STATE_REG.

Functions

cause

unsafe fn cause() -> u32

Raw reset cause for the PRO CPU.

Safety

Reads an RTC register. No side effects.

is_watchdog

const fn is_watchdog(cause: u32) -> bool

Whether a cause is one of the watchdogs.

name

const fn name(cause: u32) -> &'static str

A short name for a reset cause.

The watchdog causes are distinguished from each other deliberately: “a watchdog reset the board” is not an actionable statement when three of them exist and they are armed for different reasons.